Non-volatile memory devices, such as flash EEPROM devices, have many advantageous characteristics that make them suitable for use in low-power applications. These low-power applications include mobile device applications, such as digital cameras, MP3 music players, cellular telephones, memory cards and personal digital assistants (PDA).
As will be understood by those skilled in the art, operations to program flash EEPROM devices are typically automatically preceded by erase operations (e.g., block erasure), which prepare EEPROM cells within the devices to accept new program data. Thus, it is not uncommon for an operation to program a block of cells within an EEPROM device to be preceded by an operation to erase the block of cells to achieve a “reset” threshold voltage condition within the cells. Unfortunately, performing a relatively large number of erase operations on a block of EEPROM cells may result in the generation of “threshold-voltage” defects within one or more EEPROM cells and thereby reduce an effective lifetime of an EEPROM device.
To address an increase in the number of EEPROM cell defects that may occur in response to increases in the number of “block” erase operations performed on the EEPROM device, many EEPROM devices are configured to have one or more reserved memory blocks of EEPROM cells that operate as “redundant” memory blocks for other active memory blocks of EEPROM cells, which undergo multiple write, read and erase operations during normal use. Each of a plurality of active memory blocks that become defective during use of the EEPROM device may be replaced by a respective reserved memory block. However, once all available reserved memory blocks have been utilized to replace respective active memory blocks, then the detection of any further defects within the EEPROM device during subsequent erase and programming operations may result in device failure.
To reduce the likelihood of EEPROM device failure caused by an excessive number of erase/program operations being performed on one or more active memory blocks, techniques have been developed to relatively evenly distribute erase/program operations across all of the active memory blocks. These techniques may use flash translation layer (FTL) technology to support the relatively even distribution of erase/program operations. Nonetheless, because many of the active memory blocks may have different susceptibilities to defects caused by erase/program operations, the techniques to relatively evenly distribute erase/program operations across multiple active memory blocks may not be entirely successful in achieving relatively long device lifetimes.